SH7101 datasheet(161/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 127 of 522

REJ09B0069-0100

Table 8.9

MD0 to MD3

Bit 3

MD3

Bit 2

MD2

Bit 1

MD1

Bit 0

MD0

Description

Normal operation

Reserved (setting prohibited)

PWM mode 1

PWM mode 2*

Phase counting mode 1*

Phase counting mode 2*

Phase counting mode 3*

Phase counting mode 4*

Reset synchronous PWM mode*

Reserved (setting prohibited)

Complementary PWM mode 1 (transmit at peak)*

Complementary PWM mode 2 (transmit at trough)*

Complementary PWM mode 2 (transmit at peak and

trough)*

Legend: x: Don’t care

Notes: 1. PWM mode 2 can not be set for channels 3 and 4.

2. Phase counting mode can not be set for channels 0, 3, and 4.

3. Reset synchronous PWM mode, complementary PWM mode can only be set for

channel 3. When channel 3 is set to reset synchronous PWM mode or complementary

PWM mode, the channel 4 settings become ineffective and automatically conform to the

channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or

complementary PWM mode. Reset synchronous PWM mode and complementary PWM

mode can not be set for channels 0, 1, and 2.

8.3.3

Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU

has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.

Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is

valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM

mode 2, the output at the point at which the counter is cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

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