SH7101 datasheet(160/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 126 of 522

REJ09B0069-0100

8.3.2

Timer Mode Register (TMDR)

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of

each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings

should be changed only when TCNT operation is stopped.

Bit

Bit Name

Initial

value

R/W

Description

7, 6

—

All 1

—

Reserved

These bits are always read as 1. The write value should

always be 1.

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to operate in the normal

way, or TGRB and TGRD are to be used together for

buffer operation. When TGRD is used as a buffer

generated.

In channels 1 and 2, which have no TGRD, bit 5 is

reserved. It is always read as 0, and the write value

should always be 0.

0: TGRB and TGRD operate normally

1: TGRB and TGRD used together for buffer operation

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to operate in the normal

way, or TGRA and TGRC are to be used together for

buffer operation. When TGRC is used as a buffer

generated.

In channels 1 and 2, which have no TGRC, bit 4 is

reserved. It is always read as 0, and the write value

should always be 0.

0: TGRA and TGRD operate normally

1: TGRA and TGRC used together for buffer operation

MD3

MD2

MD1

MD0

R/W

Modes 3 to 0

These bits are used to set the timer operating mode.

See table 8.9 for details.

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