SH7101 datasheet(157/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 123 of 522

REJ09B0069-0100

Table 8.3

CCLR0 to CCLR2 (Channels 0, 3, and 4)

Channel

Bit 7

CCLR2

Bit 6

CCLR1

Bit 5

CCLR0

Description

0, 3, 4

TCNT clearing disabled

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

TCNT clearing disabled

TCNT cleared by TGRC compare match/input

capture*

TCNT cleared by TGRD compare match/input

capture*

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

Table 8.4

CCLR0 to CCLR2 (Channels 1 and 2)

Channel

Bit 7

Reserved*

Bit 6

CCLR1

Bit 5

CCLR0

Description

1, 2

TCNT clearing disabled

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.

2. Bit 7 is reserved in channels 1 and 2. It is always read as 0. Writing is ignored.

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