SH7101 datasheet(262/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 228 of 522

REJ09B0069-0100

When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to

the initial values.

TGRA_3

TCDR

TDDR

H'0000

TCNT_3

TCNT_4

Complementary PWM

mode operation

Complementary PWM

mode operation

Counter

operation stop

Complementary

PMW restart

Figure 8.79 Counter Value during Complementary PWM Mode Stop

8.7.13

Buffer Operation Setting in Complementary PWM Mode

In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting

TRGA_4, and TGRB_4).

In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit

settings BFA and BFB of TMDR_3. When TMDR_3’s BFA bit is set to 1, TGRC_3 functions as a

buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for

TRGA_4, while the TCBR functions as the TCDR’s buffer register.

8.7.14

Reset Sync PWM Mode Buffer Operation and Compare Match Flag

When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4

to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is

set to 1.

In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA

and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3

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