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SH7101 Datasheet(PDF) 261 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 261 Page - Renesas Technology Corp |
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261 / 560 page  Section 8 Multifunction Timer Pulse Unit (MTU) Rev.1.00 Sep. 18, 2008 Page 227 of 522 REJ09B0069-0100 T1 T2 H'FFFE H'FFFF N N + 1 H'FFFF M M N P QP M Disabled TCNT_2 write data TCNT_2 address TCNT write cycle P φ Address Write signal TCNT_2 TGR2A_2 to TGR2B_2 Ch2 compare- match signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare- match signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection 8.7.12 Counter Value during Complementary PWM Mode Stop When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 8.79. |
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