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SH7101 Datasheet(PDF) 265 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 265 Page - Renesas Technology Corp

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Section 8 Multifunction Timer Pulse Unit (MTU)
Rev.1.00 Sep. 18, 2008 Page 231 of 522
REJ09B0069-0100
Counter clear
signal
TCNT
TCNT input
clock
P
φ
H'FFFF
H'0000
TGF
TCFV
Disabled
Figure 8.82 Contention between Overflow and Counter Clearing
8.7.17
Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 8.83 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
Address
P
φ
TCNT address
TCNT
TCNT write cycle
T1
T2
H'FFFF
M
TCNT write data
TCFV flag
Figure 8.83 Contention between TCNT Write and Overflow



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