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SH7101 Datasheet(PDF) 296 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 296 Page - Renesas Technology Corp |
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296 / 560 page  Section 8 Multifunction Timer Pulse Unit (MTU) Rev.1.00 Sep. 18, 2008 Page 262 of 522 REJ09B0069-0100 The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 8.113. TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D POE3 POE2 POE1 POE0 Output level detection circuit Output level detection circuit Output level detection circuit Input level detection circuit Falling-edge detection circuit Low-level detection circuit OCSR ICSR1 P φ/8 P φ/16 P φ/128 High- impedance request control signal Interrupt request (MTUPOE) Legend: OCSR: Output level control/status register ICSR1: Input level control/status register Figure 8.113 POE Block Diagram |
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