SH7101 datasheet(299/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 265 of 522

REJ09B0069-0100

Bit

Bit Name

Initial

value

R/W

Description

11 to 9 —

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

PIE

R/W

Port Interrupt Enable

This bit enables/disables interrupt requests when any of

the POE0F to POE3F bits of the ICSR1 are set to 1.

0: Interrupt requests disabled

1: Interrupt requests enabled

POE3M1

POE3M0

R/W

POE3 mode 1 and 0

These bits select the input mode of the

POE3 pin.

00: Accept request on falling edge of

POE3 input.

01: Accept request when

POE3 input has been sampled

for 16 P

φ/8 clock pulses, and all are low level.

10: Accept request when

POE3 input has been sampled

for 16 P

φ/16 clock pulses, and all are low level.

11: Accept request when

POE3 input has been sampled

for 16 P

φ/128 clock pulses, and all are low level.

POE2M1

POE2M0

R/W

POE2 mode 1 and 0

These bits select the input mode of the

POE2 pin.

00: Accept request on falling edge of

POE2 input.

01: Accept request when

POE2 input has been sampled

for 16 P

φ/8 clock pulses, and all are low level.

10: Accept request when

POE2 input has been sampled

for 16 P

φ/16 clock pulses, and all are low level.

11: Accept request when

POE2 input has been sampled

for 16 P

φ/128 clock pulses, and all are low level.

POE1M1

POE1M0

R/W

POE1 mode 1 and 0

These bits select the input mode of the

POE1 pin.

00: Accept request on falling edge of

POE1 input.

01: Accept request when

POE1 input has been sampled

for 16 P

φ/8 clock pulses, and all are low level.

10: Accept request when

POE1 input has been sampled

for 16 P

φ/16 clock pulses, and all are low level.

11: Accept request when

POE1 input has been sampled

for 16 P

φ/128 clock pulses, and all are low level.

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