SH7101 datasheet(327/560 Pages) RENESAS

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Section 10 Serial Communication Interface (SCI)

Rev.1.00 Sep. 18, 2008 Page 293 of 522

REJ09B0069-0100

Table 10.2

Relationships between N Setting in BRR and Effective Bit Rate B

Mode

Asynchronous mode

(n = 0)

Asynchronous mode

(n = 1 to 3)

Clocked synchronous

mode (n = 0)

Clocked synchronous

mode (n = 1 to 3)

B0 =

φ × 106

× 22n × (N + 1)

Bit Rate

Error

B0 =

φ × 106

× 22n+1 × (N + 1)

B0 =

φ × 106

× 22n × (N + 1)

B0 =

φ × 106

× 22n+1 × (N + 1)

Error (%) =

– 1

× 100

⎞

⎠

⎞

⎠

Error (%) =

—

– 1

× 100

⎞

⎠

⎞

⎠

Note:

Effective bit rate (bit/s) Actual transfer speed according to the register settings

Logical bit rate (bit/s) Specified transfer speed of the target system

BRR setting for baud rate generator (0

≤ N ≤ 255)

φ: Peripheral clock operating frequency (MHz)

n : Determined by the SMR settings shown in the following tables.

SMR Setting

CKS1

CKS0

Table 10.3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the

maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N

settings in BRR in clocked synchronous mode. For details, refer to section 10.4.2, Receive Data

Sampling Timing and Reception Margin in Asynchronous Mode. Tables 10.5 and 10.7 show the

maximum bit rates with external clock input.

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