SH7101 datasheet(326/560 Pages) RENESAS

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Section 10 Serial Communication Interface (SCI)

Rev.1.00 Sep. 18, 2008 Page 292 of 522

REJ09B0069-0100

10.3.8

Serial Direction Control Register (SDCR)

The DIR bit in SDCR selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-

first/MSB-first selection is available regardless of the communication mode. With a 7-bit data

length, LSB-first transfer must be selected. The description in this section assumes LSB-first

transfer.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

⎯

All 1

Reserved

The write value should always be 1. Operation cannot be

guaranteed if 0 is written.

DIR

R/W

Data Transfer Direction

Selects the serial/parallel conversion format. Valid for an

8-bit transmit/receive format.

0: TDR contents are transmitted in LSB-first order

Receive data is stored in RDR in LSB-first

1: TDR contents are transmitted in MSB-first order

Receive data is stored in RDR in MSB-first

⎯

Reserved

The write value should always be 0. Operation cannot be

guaranteed if 1 is written.

⎯

Reserved

This bit is always read as 1, and cannot be modified.

⎯

Reserved

The write value should always be 0. Operation cannot be

guaranteed if 1 is written.

10.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control

independently for each channel, different bit rates can be set for each channel. Table 10.2 shows

the relationships between the N setting in BRR and the effective bit rate B

0 for asynchronous and

clocked synchronous modes. The initial value of BRR is H'FF, and it can be read from or written

to by the CPU at all times.

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