SH7101 datasheet(322/560 Pages) RENESAS

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Section 10 Serial Communication Interface (SCI)

Rev.1.00 Sep. 18, 2008 Page 288 of 522

REJ09B0069-0100

Bit

Bit Name

Initial

Value

R/W

Description

CKS1

CKS0

R/W

Clock Select 1 and 0

These bits select the clock source for the baud rate

generator.

00: P

φ clock (n = 0)

01: P

φ/8 clock (n = 1)

10: P

φ/32 clock (n = 2)

11: P

φ/128 clock (n = 3)

For the relation between the bit rate register setting and

the baud rate, see section 10.3.9, Bit Rate Register

(BRR). n is the decimal display of the value of n in BRR

(see section 10.3.9, Bit Rate Register (BRR)).

10.3.6

Serial Control Register (SCR)

SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt

requests, and selection of the transfer clock source. For details on interrupt requests, refer to

section 10.7, Interrupt Sources.

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, TXI interrupt request is enabled.

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

R/W

Transmit Enable

When this bit is set to 1, transmission is enabled.

R/W

Receive Enable

When this bit is set to 1, reception is enabled.

MPIE

R/W

Multiprocessor Interrupt Enable (enabled only when the

MP bit in SMR is 1 in asynchronous mode)

When this bit is set to 1, receive data in which the

multiprocessor bit is 0 is skipped, and setting of the

RDRF, FER, and ORER status flags in SSR is prohibited.

On receiving data in which the multiprocessor bit is 1, this

bit is automatically cleared and normal reception is

resumed. For details, refer to section 10.5,

Multiprocessor Communication Function.

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