SH7101 datasheet(324/560 Pages) RENESAS

324 / 560 page

Section 10 Serial Communication Interface (SCI)

Rev.1.00 Sep. 18, 2008 Page 290 of 522

REJ09B0069-0100

10.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot

be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/(W)*

Transmit Data Register Empty

Displays whether TDR contains transmit data.

[Setting conditions]

• Power-on reset and software standby mode

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data

can be written to TDR

[Clearing condition]

• When 0 is written to TDRE after reading TDRE = 1

RDRF

R/(W)*

Receive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

• When serial reception ends normally and receive data

is transferred from RSR to RDR

[Clearing conditions]

• Power-on reset or software standby mode

• When 0 is written to RDRF after reading RDRF = 1

The RDRF flag is not affected and retains their previous

values when the RE bit in SCR is cleared to 0.

ORER

R/(W)*

Overrun Error

[Setting condition]

• When the next serial reception is completed while

RDRF = 1

[Clearing conditions]

• Power-on reset or software standby mode

• When 0 is written to ORER after reading ORER = 1

The ORER flag is not affected and retains their previous

values when the RE bit in SCR is cleared to 0.

SH7101 Datasheet(PDF) 324 Page - Renesas Technology Corp

SH7101 Datasheet(HTML) 324 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL