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SH7101 Datasheet(PDF) 318 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 318 Page - Renesas Technology Corp |
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318 / 560 page  Section 10 Serial Communication Interface (SCI) Rev.1.00 Sep. 18, 2008 Page 284 of 522 REJ09B0069-0100 Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors detected Note: * The description in this section are based on LSB-first transfer. Figure 10.1 shows a block diagram of the SCI. RxD TxD SCK Clock P φ P φ/8 P φ/32 P φ/128 TEI TXI RXI ERI SSR SCR SMR SDCR Transmission/ reception control Baud rate generator BRR Module data bus RDR TSR RSR Parity generation Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register SDCR: Serial direction control register TDR Internal data bus Parity check External clock Figure 10.1 Block Diagram of SCI |
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