HD6433644R datasheet(35/549 Pages) RENESAS

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Section 2 CPU

Rev. 6.00 Sep 12, 2006 page 15 of 526

REJ09B0326-0600

Section 2 CPU

2.1

Overview

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit

registers. Its concise instruction set is designed for high-speed operation.

2.1.1

Features

Features of the H8/300L CPU are listed below.

• General-register architecture

Sixteen 8-bit general registers, also usable as eight 16-bit general registers

• Instruction set with 55 basic instructions, including:

 Multiply and divide instructions

 Powerful bit-manipulation instructions

• Eight addressing modes

 Register direct

 Register indirect

 Register indirect with displacement

 Register indirect with post-increment or pre-decrement

 Absolute address

 Immediate

 Program-counter relative

 Memory indirect

• 64-kbyte address space

• High-speed operation

 All frequently used instructions are executed in two to four states

 High-speed arithmetic and logic operations

8- or 16-bit register-register add or subtract: 0.4 µs (operating at

φ = 5 MHz)

0.25 µs (operating at

φ = 8 MHz)*

× 8-bit multiply:

2.8 µs (operating at

φ = 5 MHz)

1.75 µs (operating at

φ = 8 MHz)*

16 ÷ 8-bit divide:

2.8 µs (operating at

φ = 5 MHz)

1.75 µs (operating at

φ = 8 MHz)*

Note: * Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version.

HD6433644R Datasheet(PDF) 35 Page - Renesas Technology Corp

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