HD6433644R datasheet(39/549 Pages) RENESAS

39 / 549 page

Section 2 CPU

Rev. 6.00 Sep 12, 2006 page 19 of 526

REJ09B0326-0600

Condition Code Register (CCR): This 8-bit register contains internal status information,

including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and

carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC,

ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for

conditional branching (Bcc) instructions.

Bit 7

Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1

automatically at the start of exception handling. The interrupt mask bit may be read and written by

software. For further details, see section 3.3, Interrupts.

Bit 6

User Bit (U): Can be used freely by the user.

Bit 5

Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0

otherwise.

The H flag is used implicitly by the DAA and DAS instructions.

When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a

carry or borrow at bit 11, and is cleared to 0 otherwise.

Bit 4

User Bit (U): Can be used freely by the user.

Bit 3VNegative Flag (N): Indicates the most significant bit (sign bit) of the result of an

instruction.

Bit 2

Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero

result.

Bit 1

Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0

Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift/rotate carry

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave some or all of the flag bits unchanged.

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