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HD6433644R Datasheet(PDF) 92 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 92 Page - Renesas Technology Corp |
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92 / 549 page  Section 3 Exception Handling Rev. 6.00 Sep 12, 2006 page 72 of 526 REJ09B0326-0600 3.3.4 Internal Interrupts There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0. All these interrupts can be masked by setting the I bit to 1 in CCR. When internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 23 to 9 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt controller Interrupt request CCR (CPU) I External or internal interrupts External interrupts or internal interrupt enable signals Figure 3.2 Block Diagram of Interrupt Controller |
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