HD6433644R datasheet(79/549 Pages) RENESAS

79 / 549 page

Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 59 of 526

REJ09B0326-0600

Section 3 Exception Handling

3.1

Overview

Exception handling is performed in the H8/3644 Group when a reset or interrupt occurs. Table 3.1

shows the priorities of these two types of exception handling.

Table 3.1

Exception Handling Types and Priorities

Priority

Exception Source

Time of Start of Exception Handling

High

Reset

Exception handling starts as soon as the reset state is cleared

Low

Interrupt

When an interrupt is requested, exception handling starts after

execution of the present instruction or the exception handling

in progress is completed

3.2

Reset

3.2.1

Overview

A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-

chip peripheral modules are initialized.

3.2.2

Reset Sequence

Reset by

RES

RES Pin: As soon as the RES pin goes low, all processing is stopped and the chip enters

the reset state.

To make sure the chip is reset properly, observe the following precautions.

• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.

• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.

Reset exception handling begins when the

RES pin is held low for a given period, then returned to

the high level.

HD6433644R Datasheet(PDF) 79 Page - Renesas Technology Corp