HD6433644R datasheet(88/549 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 68 of 526

REJ09B0326-0600

Interrupt Request Register 1 (IRR1)

Bit

IRRTB1

IRRTA



IRRI3

IRRI2

IRRI1

IRRI0

Initial value

Read/Write

R/W*



R/W*

Note:

* Only a write of 0 for flag clearing is possible.

IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer B1,

timer A, or IRQ3 to IRQ0 interrupt is requested. The flags are not cleared automatically when an

interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR1 is initialized to

H'10.

Bit 7



Timer B1 Interrupt Request Flag (IRRTB1)

Bit 7: IRRTB1

Description

Clearing condition:

(initial value)

When IRRTB1 = 1, it is cleared by writing 0

Setting condition:

When the timer B1 counter value overflows from H'FF to H'00

Bit 6



Timer A Interrupt Request Flag (IRRTA)

Bit 6: IRRTA

Description

Clearing condition:

(initial value)

When IRRTA = 1, it is cleared by writing 0

Setting condition:

When the timer A counter value overflows from H'FF to H'00

Bit 5



Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.

Bit 4



Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.

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