HD6433644R datasheet(87/549 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 67 of 526

REJ09B0326-0600

Bit 6



A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter

interrupt requests.

Bit 6: IENAD

Description

Disables A/D converter interrupt requests

(initial value)

Enables A/D converter interrupt requests

Bit 5



Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.

Bit 4



SCI1 Interrupt Enable (IENS1): Bit 4 enables or disables SCI1 transfer complete

interrupt requests.

Bit 4: IENS1

Description

Disables SCI1 interrupt requests

(initial value)

Enables SCI1 interrupt requests

Bits 3 to 0



Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be

modified.

Interrupt Enable Register 3 (IENR3)

Bit

INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0

Initial value

Read/Write

R/W

IENR3 is an 8-bit read/write register that enables or disables INT7 to INT0 interrupt requests.

Upon reset, IENR3 is initialized to H'00.

Bits 7 to 0



INT7 to INT0 Interrupt Enable (INTEN7 to INTEN0): Bits 7 to 0 enable or

disable INT7 to INT0 interrupt requests.

Bit n: INTENn

Description

Disables interrupt requests from pin

INTn

(initial value)

Enables interrupt requests from pin

INTn

(n = 7 to 0)

HD6433644R Datasheet(PDF) 87 Page - Renesas Technology Corp

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