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HD6433644R Datasheet(PDF) 84 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 84 Page - Renesas Technology Corp |
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84 / 549 page ![]() Section 3 Exception Handling Rev. 6.00 Sep 12, 2006 page 64 of 526 REJ09B0326-0600 Bit 2 IRQ2 Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ2. Bit 2: IEG2 Description 0 Falling edge of IRQ2 pin input is detected (initial value) 1 Rising edge of IRQ2 pin input is detected Bit 1 IRQ1 Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ1. Bit 1: IEG1 Description 0 Falling edge of IRQ1 pin input is detected (initial value) 1 Rising edge of IRQ1 pin input is detected Bit 0 IRQ0 Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ0. Bit 0: IEG0 Description 0 Falling edge of IRQ0 pin input is detected (initial value) 1 Rising edge of IRQ0 pin input is detected Interrupt Edge Select Register 2 (IEGR2) Bit 7 6 5 4 3 2 1 0 INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IEGR2 is an 8-bit read/write register, used to designate whether pins INT 7 to INT0, and TMIB are set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'00. Bit 7 INT7 Edge Select (INTEG7): Bit 7 selects the input sensing of the INT7 pin. Bit 7: INTEG7 Description 0 Falling edge of INT7 pin input is detected (initial value) 1 Rising edge of INT7 pin input is detected |
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