HD6433644R datasheet(83/549 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 63 of 526

REJ09B0326-0600

3.3.2

Interrupt Control Registers

Table 3.3 lists the registers that control interrupts.

Table 3.3

Interrupt Control Registers

Name

Abbreviation

R/W

Initial Value

Address

Interrupt edge select register 1

IEGR1

R/W

H'70

H'FFF2

Interrupt edge select register 2

IEGR2

R/W

H'00

H'FFF3

Interrupt enable register 1

IENR1

R/W

H'10

H'FFF4

Interrupt enable register 2

IENR2

R/W

H'00

H'FFF5

Interrupt enable register 3

IENR3

R/W

H'00

H'FFF6

Interrupt request register 1

IRR1

R/W*

H'10

H'FFF7

Interrupt request register 2

IRR2

R/W*

H'00

H'FFF8

Interrupt request register 3

IRR3

R/W*

H'00

H'FFF9

Note:

* Write is enabled only for writing of 0 to clear a flag.

Interrupt Edge Select Register 1 (IEGR1)

Bit



IEG3

IEG2

IEG1

IEG0

Initial value

Read/Write



R/W

IEGR1 is an 8-bit read/write register used to designate whether pins

IRQ

3 to IRQ0 are set to rising

edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70.

Bit 7



Reserved Bit: Bit 7 is reserved: it is always read as 0 and cannot be modified.

Bits 6 to 4



Reserved Bits: Bits 6 to 4 are reserved; they are always read as 1, and cannot be

modified.

Bit 3



IRQ3 Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ3.

Bit 3: IEG3

Description

Falling edge of

IRQ3 pin input is detected

(initial value)

Rising edge of

IRQ3 pin input is detected

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