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HD6433644R Datasheet(PDF) 65 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 65 Page - Renesas Technology Corp |
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65 / 549 page ![]() Section 2 CPU Rev. 6.00 Sep 12, 2006 page 45 of 526 REJ09B0326-0600 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Two-State Access to On-Chip Peripheral Modules: Figure 2.12 shows the operation timing in the case of two-state access to an on-chip peripheral module. T1 state Bus cycle T2 state φ or φ Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Write data Internal data bus (write access) SUB Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access) |
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