HD6433644R datasheet(90/549 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 70 of 526

REJ09B0326-0600

Bit 5

Reserved bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.

Bit 4

SCI1 Interrupt Request Flag (IRRS1)

Bit 4: IRRS1

Description

Clearing condition:

(initial value)

When IRRS1 = 1, it is cleared by writing 0

Setting condition:

When an SCI1 transfer is completed

Bits 3 to 0

Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be

modified.

Interrupt Request Register 3 (IRR3)

Bit

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

Initial value

Read/Write

R/W*

Note:

* Only a write of 0 for flag clearing is possible.

IRR3 is an 8-bit read/write register, in which a corresponding flag is set to 1 by a transition at pin

INT

7 to INT0. The flags are not cleared automatically when an interrupt is accepted. It is necessary

to write 0 to clear each flag. Upon reset, IRR3 is initialized to H'00.

Bits 7 to 0

INT7 to INT0 Interrupt Request Flags (INTF7 to INTF0)

Bit n: INTFn

Description

Clearing condition:

(initial value)

When INTFn = 1, it is cleared by writing 0

Setting condition:

When the designated signal edge is input at pin

INTn

(n = 7 to 0)

HD6433644R Datasheet(PDF) 90 Page - Renesas Technology Corp

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