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HD6433644R Datasheet(PDF) 66 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 66 Page - Renesas Technology Corp |
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66 / 549 page  Section 2 CPU Rev. 6.00 Sep 12, 2006 page 46 of 526 REJ09B0326-0600 Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in the case of three-state access to an on-chip peripheral module. T1 state Bus cycle Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Internal data bus (write access) T2 state T3 state Write data SUB φ or φ Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14. Figure 2.15 shows the state transitions. |
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