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HD6433644R Datasheet(PDF) 67 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 67 Page - Renesas Technology Corp |
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67 / 549 page ![]() Section 2 CPU Rev. 6.00 Sep 12, 2006 page 47 of 526 REJ09B0326-0600 CPU state Reset state Program execution state Program halt state Exception- handling state Active (high speed) mode Active (medium speed) mode Subactive mode Sleep (high-speed) mode Standby mode Watch mode Subsleep mode Low-power modes The CPU executes successive program instructions at high speed, synchronized by the system clock The CPU executes successive program instructions at reduced speed, synchronized by the system clock The CPU executes successive program instructions at reduced speed, synchronized by the subclock A state in which some or all of the chip functions are stopped to conserve power A transient state in which the CPU changes the processing flow due to a reset or an interrupt The CPU is initialized Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Sleep (medium-speed) mode Figure 2.14 CPU Operation States |
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