HD6433644R datasheet(99/549 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 79 of 526

REJ09B0326-0600

3.4.2

Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins, the

following points should be observed.

When an external interrupt pin function is switched by rewriting the port mode register that

controls pins

IRQ

3 to IRQ1, the interrupt request flag may be set to 1 at the time the pin function is

switched, even if no valid interrupt is input at the pin. Table 3.5 shows the conditions under which

interrupt request flags are set to 1 in this way.

Table 3.5

Conditions under which Interrupt Request Flag Is Set to 1

Interrupt Request

Flags Set to 1

Conditions

IRR1

IRRI3

When PMR1 bit IRQ3 is changed from 0 to 1 while pin

IRQ3 is low and

IEGR bit IEG3 = 0.

When PMR1 bit IRQ3 is changed from 1 to 0 while pin

IRQ3 is low and

IEGR bit IEG3 = 1.

IRRI2

When PMR1 bit IRQ2 is changed from 0 to 1 while pin

IRQ2 is low and

IEGR bit IEG2 = 0.

When PMR1 bit IRQ2 is changed from 1 to 0 while pin

IRQ2 is low and

IEGR bit IEG2 = 1.

IRRI1

When PMR1 bit IRQ1 is changed from 0 to 1 while pin

IRQ1 is low and

IEGR bit IEG1 = 0.

When PMR1 bit IRQ1 is changed from 1 to 0 while pin

IRQ1 is low and

IEGR bit IEG1 = 1.

Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt

request flag.

When switching a pin function, mask the interrupt before setting the bit in the port mode register.

After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the

interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after

the port mode register access without executing an intervening instruction, the flag will not be

cleared.

An alternative method is to avoid the setting of interrupt request flags when pin functions are

switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.

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