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HD6433644R Datasheet(PDF) 80 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 80 Page - Renesas Technology Corp |
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80 / 549 page  Section 3 Exception Handling Rev. 6.00 Sep 12, 2006 page 60 of 526 REJ09B0326-0600 Reset exception handling takes place as follows. • The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. • The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. Vector fetch φ Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) RES Internal processing Program initial instruction prefetch (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program (2) (3) (2) (1) Reset cleared Figure 3.1 Reset Sequence |
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