HD6433644R datasheet(86/549 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 66 of 526

REJ09B0326-0600

Bit 6



Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt

requests.

Bit 6: IENTA

Description

Disables timer A interrupt requests

(initial value)

Enables timer A interrupt requests

Bit 5



Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.

Bit 4



Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.

Bits 3 to 0



IRQ3 to IRQ0 Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable IRQ3

to IRQ0 interrupt requests.

Bit n: IENn

Description

Disables interrupt requests from pin

IRQn

(initial value)

Enables interrupt requests from pin

IRQn

(n = 3 to 0)

Interrupt Enable Register 2 (IENR2)

Bit

IENDT

IENAD



IENS1



Initial value

Read/Write

R/W



R/W



IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR2

is initialized to H'00.

Bit 7



Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer

interrupt requests.

Bit 7: IENDT

Description

Disables direct transfer interrupt requests

(initial value)

Enables direct transfer interrupt requests

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