HD6433644R datasheet(54/549 Pages) RENESAS

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Section 2 CPU

Rev. 6.00 Sep 12, 2006 page 34 of 526

REJ09B0326-0600

2.5.3

Logic Operations

Table 2.6 describes the four instructions that perform logic operations.

Table 2.6

Logic Operation Instructions

Instruction

Size*

Function

AND

∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another

general register or immediate data

∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general register or immediate data

XOR

⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data

NOT

~ Rd

→ Rd

Obtains the one’s complement (logical complement) of general

Notes: * Size: Operand size

B: Byte

2.5.4

Shift Operations

Table 2.7 describes the eight shift instructions.

Table 2.7

Shift Instructions

Instruction

Size*

Function

SHAL

SHAR

Rd shift

→ Rd

Performs an arithmetic shift operation on general register contents

SHLL

SHLR

Rd shift

→ Rd

Performs a logical shift operation on general register contents

ROTL

ROTR

Rd rotate

→ Rd

Rotates general register contents

ROTXL

ROTXR

Rd rotate

→ Rd

Rotates general register contents through the C (carry) bit

Notes: * Size: Operand size

B: Byte

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