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HD6433644R Datasheet(PDF) 45 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 45 Page - Renesas Technology Corp |
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45 / 549 page  Section 2 CPU Rev. 6.00 Sep 12, 2006 page 25 of 526 REJ09B0326-0600 2.4.2 Effective Address Calculation Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position. |
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