HD6433644R datasheet(85/549 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Sep 12, 2006 page 65 of 526

REJ09B0326-0600

Bit 6



INT6 Edge Select (INTEG6): Bit 6 selects the input sensing of the INT6 pin and TMIB

pin.

Bit 6: INTEG6

Description

Falling edge of

INT6 and TMIB pin input is detected

(initial value)

Rising edge of

INT6 and TMIB pin input is detected

Bit 5



INT5 Edge Select (INTEG5): Bit 5 selects the input sensing of the INT5 pin and ADTRG

pin.

Bit 5: INTEG5

Description

Falling edge of

INT5 and ADTRG pin input is detected

(initial value)

Rising edge of

INT5 and ADTRG pin input is detected

Bits 4 to 0



INT4 to INT0 Edge Select (INTEG4 to INTEG0): Bits 4 to 0 select the input

sensing of pins

INT

4 to INT0.

Bit n: INTEGn

Description

Falling edge of

INTn pin input is detected

(initial value)

Rising edge of

INTn pin input is detected

(n = 4 to 0)

Interrupt Enable Register 1 (IENR1)

Bit

IENTB1

IENTA



IEN3

IEN2

IEN1

IEN0

Initial value

Read/Write

R/W



R/W

IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1

is initialized to H'10.

Bit 7



Timer B1 Interrupt Enable (IENTB1): Bit 7 enables or disables timer B1 overflow

interrupt requests.

Bit 7: IENTB1

Description

Disables timer B1 interrupt requests

(initial value)

Enables timer B1 interrupt requests

HD6433644R Datasheet(PDF) 85 Page - Renesas Technology Corp

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