HD6433644R datasheet(22/549 Pages) RENESAS

22 / 549 page

Section 1 Overview

Rev. 6.00 Sep 12, 2006 page 2 of 526

REJ09B0326-0600

Table 1.1

Features

Item

Description

CPU

High-speed H8/300L CPU

• General-register architecture

General registers: Sixteen 8-bit registers (can be used as eight 16-bit

registers)

• Operating speed

 Max. operation speed: 5 MHz (mask ROM and ZTAT versions)

8 MHz (Applies only to F-ZTAT, R of the ZTAT,

and R of the mask ROM version)

 Add/subtract: 0.4 µs (operating at φ = 5 MHz)

0.25 µs (operating at

φ = 8 MHz)*

 Multiply/divide: 2.8 µs (operating at φ = 5 MHz)

1.75 µs (operating at

φ = 8 MHz)*

 Can run on 32.768 kHz subclock

• Instruction set compatible with H8/300 CPU

 Instruction length of 2 bytes or 4 bytes

 Basic arithmetic operations between registers

 MOV instruction for data transfer between memory and registers

• Typical instructions

 Multiply (8 bits × 8 bits)

 Divide (16 bits ÷ 8 bits)

 Bit accumulator

 Register-indirect designation of bit position

Interrupts

33 interrupt sources

• 12 external interrupt sources (IRQ3 to IRQ0, INT7 to INT0)

• 21 internal interrupt sources

Clock pulse

generators

Two on-chip clock pulse generators

• System clock pulse generator:

1 to 10 MHz (1 to 16 MHz*

 Crystal or ceramic resonator: 2 to 10 MHz (2 to 16 MHz*

 External clock input:

1 to 10 MHz (1 to 16 MHz*

• Subclock pulse generator:

32.768 kHz

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