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HD6433644R Datasheet(PDF) 55 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 55 Page - Renesas Technology Corp |
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55 / 549 page ![]() Section 2 CPU Rev. 6.00 Sep 12, 2006 page 35 of 526 REJ09B0326-0600 Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn ADD, SUB, CMP, ADDX, SUBX (Rm) Legend: op: rm, rn: IMM: Operation field Register field Immediate data 15 0 87 op rn ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 15 0 87 op rn MULXU, DIVXU rm 15 0 87 rn IMM ADD, ADDX, SUBX, CMP (#XX:8) op 15 0 87 op rn AND, OR, XOR (Rm) rm 15 0 87 rn IMM AND, OR, XOR (#xx:8) op 15 0 87 rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR op Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes |
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