HD6433644R datasheet(101/549 Pages) RENESAS

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Section 4 Clock Pulse Generators

Rev. 6.00 Sep 12, 2006 page 81 of 526

REJ09B0326-0600

Section 4 Clock Pulse Generators

4.1

Overview

Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a

system clock pulse generator and a subclock pulse generator. The system clock pulse generator

consists of a system clock oscillator and system clock dividers. The subclock pulse generator

consists of a subclock oscillator circuit and a subclock divider.

4.1.1

Block Diagram

Figure 4.1 shows a block diagram of the clock pulse generators.

System clock

oscillator

System clock

divider (1/2)

Subclock

oscillator

Subclock

divider

(1/2, 1/4, 1/8)

System clock

divider

(1/64, 1/32,

1/16, 1/8)

System clock pulse generator

Subclock pulse generator

Prescaler S

(13 bits)

Prescaler W

(5 bits)

OSC

)

OSC

(f )

OSC

φ /2

φ /8

SUB

φ/2

φ/8192

φ /2

φ /4

φ /8

φ /128

φOSC/128

φOSC/64

φOSC/32

φOSC/16

φ /4

Figure 4.1 Block Diagram of Clock Pulse Generators

4.1.2

System Clock and Subclock

The basic clock signals that drive the CPU and on-chip peripheral modules are

φ and φSUB. Four of

the clock signals have names:

φ is the system clock, φSUB is the subclock, φOSC is the oscillator

clock, and

φW is the watch clock.

The clock signals available for use by peripheral modules are

φ/2, φ/4, φ/8, φ/16, φ/32, φ/64,

φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φW/2, φW/4, φW/8, φW/16, φW/32, φW/64, and

φW/128. The clock requirements differ from one module to another.

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