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HD6433644R Datasheet(PDF) 351 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 351 Page - Renesas Technology Corp |
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351 / 549 page ![]() Section 10 Serial Communication Interface Rev. 6.00 Sep 12, 2006 page 331 of 526 REJ09B0326-0600 Start End Read bit TDRE in SSR 1 3 2 Set bit MPBT in SSR Write transmit data to TDR Read bit TEND in SSR Clear bit TE to 0 in SCR3 Set PDR = 0, PCR = 1 Yes TDRE = 1? No Continue data transmission? No TEND = 1? Break output? No Yes Yes No Yes Read the serial status register (SSR) and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TE in SCR3 to 0. 1. 2. 3. Figure 10.22 Example of Multiprocessor Data Transmission Flowchart |
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