HD6433644R datasheet(357/549 Pages) RENESAS

357 / 549 page

Section 10 Serial Communication Interface

Rev. 6.00 Sep 12, 2006 page 337 of 526

REJ09B0326-0600

For further details, see section 3.3, Interrupts.

10.3.8

Application Notes

The following points should be noted when using SCI3.

1. Relation between writes to TDR and bit TDRE

Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial

transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared

to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.

Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to

TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has

not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed

dependably, you should first check that bit TDRE is set to 1, then write the transmit data to

TDR once only (not two or more times).

2. Operation when a number of receive errors occur simultaneously

If a number of receive errors are detected simultaneously, the status flags in SSR will be set to

the states shown in table 10.17. If an overrun error is detected, data transfer from RSR to RDR

will not be performed, and the receive data will be lost.

Table 10.17 SSR Status Flag States and Receive Data Transfer

SSR Status Flags

Receive Data Transfer

RDRF* OER

FER

PER

(RSR

→

→ RDR)

Receive Error Status

Overrun error

Framing error

Parity error

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

Overrun error + framing error + parity error

Legend:

O: Receive data is transferred from RSR to RDR.

× : Receive data is not transferred from RSR to RDR.

Note:

* Bit RDRF retains its state prior to data reception.

HD6433644R Datasheet(PDF) 357 Page - Renesas Technology Corp

HD6433644R Datasheet(HTML) 357 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL