HD6433644R datasheet(363/549 Pages) RENESAS

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Section 11 14-Bit PWM

Rev. 6.00 Sep 12, 2006 page 343 of 526

REJ09B0326-0600

Bit 0



Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a

write-only bit; it is always read as 1.

Bit 0: PWCR0

Description

The input clock is

φ/2 (tφ* = 2/φ). The conversion period is 16,384/φ, with

a minimum modulation width of 1/

(initial value)

The input clock is

φ/4 (tφ* = 4/φ). The conversion period is 32,768/φ, with

a minimum modulation width of 2/

φ.

Note:

* tφ Period of PWM input clock

11.2.2

PWM Data Registers U and L (PWDRU, PWDRL)

PWDRU

Bit



PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0

Initial value

Read/Write



PWDRL

Bit

PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0

Initial value

Read/Write

PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU

and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total high-

level width of one PWM waveform cycle.

When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM

waveform generator, updating the PWM waveform generation data. The 14-bit data should always

be written in the following sequence:

1. Write the lower 8 bits to PWDRL.

2. Write the upper 6 bits to PWDRU.

PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.

HD6433644R Datasheet(PDF) 363 Page - Renesas Technology Corp

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