HD6433644R datasheet(106/549 Pages) RENESAS

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Section 4 Clock Pulse Generators

Rev. 6.00 Sep 12, 2006 page 86 of 526

REJ09B0326-0600

In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse

generator stops. Prescaler S also stops and is initialized to H'0000.

The CPU cannot read or write prescaler S.

The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be

set separately for each on-chip peripheral function.

In active (medium-speed) mode the clock input to prescaler S is determined by the division factor

designated by MA1 and MA0 in SYSCR1.

Prescaler W (PSW): Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (

φW/4)

as its input clock.

Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.

Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues

functioning so long as clock signals are supplied to pins X1 and X2.

Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).

Output from prescaler W can be used to drive timer A, in which case timer A functions as a time

base for timekeeping.

4.5

Note on Oscillators

Oscillator characteristics are closely related to board design and should be carefully evaluated by

the user, referring to the examples shown in this section. Oscillator circuit constants will differ

depending on the oscillator element, stray capacitance in its interconnecting circuit, and other

factors. Suitable constants should be determined in consultation with the oscillator element

manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding

its maximum rating.

HD6433644R Datasheet(PDF) 106 Page - Renesas Technology Corp