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HD6433644R Datasheet(PDF) 197 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 197 Page - Renesas Technology Corp |
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197 / 549 page ![]() Section 8 I/O Ports Rev. 6.00 Sep 12, 2006 page 177 of 526 REJ09B0326-0600 8.3 Port 2 8.3.1 Overview Port 2 is a 3-bit I/O port, configured as shown in figure 8.2. P2 /TXD P2 /RXD P2 /SCK 2 1 0 Port 2 3 Figure 8.2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration. Table 8.5 Port 2 Registers Name Abbr. R/W Initial Value Address Port data register 2 PDR2 R/W H'00 H'FFD5 Port control register 2 PCR2 W H'00 H'FFE5 Port Data Register 2 (PDR2) Bit 7 6 5 4 3 2 1 0 P22 P21 P20 Initial value 0* 0* 0* 0* 0* 0 0 0 Read/Write R/W R/W R/W Note: * Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified. PDR2 is an 8-bit register that stores data for port 2 pins P22 to P20. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read. Upon reset, PDR2 is initialized to H'00. |
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