SH7785 datasheet(120/1692 Pages) RENESAS

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5. Exception Handling

Rev.1.00 Jan. 10, 2008 Page 90 of 1658

REJ09B0261-0100

Table 5.2

States of Register in Each Operating Mode

Abbr.

Power-on

Reset

Manual Reset Sleep

Standby

TRAPA exception register

TRA

Undefined

Retained

Exception event register

EXPEVT

H'0000 0000 H'0000 0020

Retained

Interrupt event register

INTEVT

Undefined

Retained

Non-support detection exception

EXPMASK H'0000 0013 H'0000 0013

Retained

5.2.1

TRAPA Exception Register (TRA)

The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA

instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA

can also be modified by software.

Bit:

0000000000000000

Initial value:

RRRRRRRRRRRRRRRR

R/W

TRACODE

R/W

R/W:

Bit:

Initial value:

R/W:

9876543210

RRRRRR

R/W

Bit

Bit Name

Initial Value

R/W

Description

31 to 10

⎯

All 0

Reserved

For details on reading/writing this bit, see General

Precautions on Handling of Product.

9 to 2

TRACODE

Undefined

R/W

TRAPA Code

8-bit immediate data of TRAPA instruction is set

1, 0

⎯

All 0

Reserved

For details on reading/writing this bit, see General

Precautions on Handling of Product.

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