SH7785 datasheet(121/1692 Pages) RENESAS

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5. Exception Handling

Rev.1.00 Jan. 10, 2008 Page 91 of 1658

REJ09B0261-0100

5.2.2

Exception Event Register (EXPEVT)

The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code

set in EXPEVT is that for a reset or general exception event. The exception code is set

automatically by hardware when an exception occurs. EXPEVT can also be modified by software.

Bit:

0000000000000000

000000

0/1

00000

Initial value:

RRRRRRRRRRRRRRRR

R/W

EXPCODE

R/W

R/W:

Bit:

Initial value:

R/W:

9876543210

0000

R/W

Bit

Bit Name

Initial

Value

R/W

Description

31 to 12

⎯

All 0

Reserved

For details on reading/writing this bit, see General

Precautions on Handling of Product.

11 to 0

EXPCODE

H'000 or

H'020

R/W

Exception Code

The exception code for a reset or general exception is

set. For details, see table 5.3.

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