SH7021 datasheet(160/509 Pages) RENESAS

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142 RENESAS

8.5.5

DRAM Burst Mode

In addition to the normal mode of DRAM access, in which row addresses are output at every

access and data then accessed (full access), the DRAM also has a high-speed page mode for use

when continuously accessing the same row. The high speed page mode enables fast access of data

simply by changing the column address after the row address is output (burst mode). Select

between full access and burst operation by setting the burst enable bit (BE)) in the DCR. When the

BE bit is set to 1, burst operation is performed when the row address matches the previous DRAM

access row address. Figure 8.22 shows the comparison of full access and burst operation.

RAS

CAS

AD15–

AD0

RAS

CAS

A21–A0

AD15–

AD0

A21–A0

Row address 1

Column address 1

Row address 2

Column

address 2

Data 1

Data 2

Row address 1

Column

address 1

Column

address 2

Column

address 3

Column

address 4

Data 1

Data 2

Data 3

Data 4

(a) Full access (read cycle)

(b) Burst operation (read cycle)

Figure 8.22 Full Access and Burst Operation

Short pitch high-speed page mode or long pitch high-speed page mode burst transfers can be

selected independently for DRAM read/write cycles even when the burst operation is selected by

using the bits corresponding to area 1 in WCR1 and WCR2 (RW1, WW1, DRW1, DWW1). The

RAS down mode or RAS up mode can be selected by setting the RAS down bit (RASD) of the

DCR when there is an access outside the DRAM space during burst operation.

SH7021 Datasheet(PDF) 160 Page - Renesas Technology Corp

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