SH7021 datasheet(161/509 Pages) RENESAS

161 / 509 page

RENESAS 143

Short Pitch High-Speed Page Mode and Long Pitch High-Speed Page Mode: When burst

operation is selected by setting the DCR’s BE bit to 1, the short pitch high-speed page mode or

long pitch high-speed page mode can be selected by setting the RW1, WW1, DRW1, and DWW1

bits of the WCR1 and WCR2.

•

Short-pitch, high-speed page mode: When the RW1, WW1, DRW1 and DWW1 bits in the

WCR1 and WCR2 are cleared to 0, and the corresponding DRAM access cycle is continuing,

the

CAS signal and column address output cycles continue as long as the row addresses

continue to match. The column address output cycle is performed in 1 state and the

WAIT

signal is not sampled. Figure 8.23 shows the read cycle timing for the short pitch high-speed

page mode.

A21–

RAS

CAS

Data 4

Data 3

Data 2

Data 1

AD15–

Column

address 1

Column

address 2

Column

address 3

Column

address 4

Row address 1

Figure 8.23 Short Pitch High-Speed Page Mode (Read Cycle)

When the write cycle continues for the same row address in the short pitch high-speed page

mode, an open cycle (silent cycle) is produced for 1 cycle only. This timing is shown in figure

8.24. Likewise, when a write cycle continues after the read cycle for the same row address, a

silent cycle is produced for 1 cycle. This timing is shown in figure 8.25. Note also that when

DRAM is written to in short-pitch, high-speed page mode when using DMAC single address

mode, a silent cycle is inserted in each transfer. The details of timing are discussed in section

20.3.3, Bus Timing.

SH7021 Datasheet(PDF) 161 Page - Renesas Technology Corp