SH7021 datasheet(202/509 Pages) RENESAS

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source or destination. When RXI is set as the transfer request, however, the transfer source must

be the SCI’s receive data register (RDR). Likewise, when TXI is set as the transfer request, the

transfer source must be the SCI's transmit data register (TDR).

Table 9.4

Selecting On-Chip Peripheral Module Request Modes with the RS Bit

RS3

RS2 RS1

RS0

DMA

Transfer

Request

Source

DMA Transfer Request

Signal

Source

Desti-

nation

Bus Mode

SCI0

receiver

RXI0 (SCI0 receive data full

interrupt transfer request)

RDR0

Any*

Cycle steal

SCI0

trans-

mitter

TXI0 (SCI0 transmit data

empty interrupt transfer

request)

Any

TDR0

Cycle steal

SCI1

receiver

RXI1 (SCI1 receive data full

interrupt transfer request)

RDR1

Any*

Cycle steal

SCI1

trans-

mitter

TXI1 (SCI1 transmit data

empty interrupt transfer

request)

Any*

TDR1

Cycle steal

ITU0

IMIA0 (ITU0 input capture A/

compare-match A)

Any*

Burst/Cycle

steal

ITU1

IMIA1 (ITU1 input capture A/

compare-match A)

Any*

Burst/Cycle

steal

ITU2

IMIA2 (ITU2 input capture A/

compare-match A)

Any*

Burst/Cycle

steal

ITU3

IMIA3 (ITU3 input capture A/

compare-match A)

Any*

Burst/Cycle

steal

SCI0, SCI1: Serial communications interface channels 0 and 1

ITU0–ITU3: Channels 0–3 of the 16-bit integrated-timer pulse unit.

RDR0, RDR1: Receive data registers 0, 1 of SCI

TDR0, TDR1: Transmit data registers 0, 1 of SCI

Note:

External memory, memory-mapped external device, on-chip memory, on-chip peripheral

module (excluding DMAC)

When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt

enable bits must be set to output the interrupt signals. Note that transfer request signals from on-

chip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU

as well. When an on-chip peripheral module is specified as the transfer request source, set the

priority level values in the interrupt priority level registers (IPRC–IPRE) of the interrupt controller

(INTC) at or below the levels set in the I3–I0 bits of the CPU’s status register (SR) so that the

CPU does not acknowledge the interrupt request signal.

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