SH7021 datasheet(203/509 Pages) RENESAS

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The DMA transfer request signals of table 9.4 are automatically withdrawn when the

corresponding DMA transfer is performed. If the cycle steal mode is being employed, the DMA

transfer request (interrupt request) will be cleared at the first transfer; if the burst mode is being

used, it will be cleared at the last transfer.

9.3.3

Channel Priority

When the DMAC receives simultaneous transfer requests on two or more channels, it selects a

channel according to a predetermined priority order. The three modes (fixed mode, round-robin

mode, and external-pin round-robin mode) are selected by the priority bits PR1 and PR0 in the

DMA operation register.

Fixed Mode: In these modes, the priority levels among the channels remain fixed. When PR1 and

PR0 bits are set 00, the priority order, high to low, is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1. When PR1

and PR0 bits are set 01, the priority order, high to low, is Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0.

Round-Robin Mode: Each time one word or byte is transferred on one channel, the priority order

is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority

order. When necessary, the priority order of channels other than the one that just finished the

transfer can also be shifted to keep the relationship between the channels from changing (figure

9.3). The priority order immediately after a reset is channel 0 > channel 3 > channel 2 > channel 1.

SH7021 Datasheet(PDF) 203 Page - Renesas Technology Corp