SH7021 datasheet(215/509 Pages) RENESAS

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with higher priority (2) will begin immediately. When channel 2 is also operating in the burst

mode, the channel 1 transfer will continue when the channel 2 transfer has completely finished.

When channel 2 is in the cycle steal mode, channel 1 will begin operating again after channel 2

completes the transfer of one transfer unit, but the bus will then switch between the two in the

order channel 1, channel 2, channel 1, channel 2. Since channel 1 is in burst mode, it will not give

the bus to the CPU. This example is illustrated in figure 9.12.

CPU

Bus

status

DMAC

ch1

DMAC

ch1

DMAC

ch2

DMAC

ch1

DMAC

ch2

DMAC

ch1

DMAC

ch1

CPU

ch2

ch1

ch2

DMAC ch1 and ch2

Cycle steal mode

DMAC ch1

Burst mode

CPU

DMAC ch1

Burst mode

Figure 9.12 Bus Handling when Multiple Channels Are Operating

9.3.5

Number of Bus Cycle States and

DREQ Pin Sample Timing

Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the

bus master is controlled by the bus state controller just as it is when the CPU is the bus master.

The bus cycle in the dual address mode is controlled by wait state control register 1 (WCR1) while

the single address mode bus cycle is controlled by wait state control register 2 (WCR2). For

details, see section 8.9, Wait State Control.

DREQ Pin Sampling Timing: Normally, when DREQ input is detected immediately prior to the

rise edge of the clock pulse (CK) in external request mode, a DMAC bus cycle will be generated

and the DMA transfer performed two states later at the earliest. The sampling timing after

DREQ

input detection differs by bus mode, address mode and method of

DREQ input detection.

•

DREQ pin sampling timing in the cycle steal mode

In the cycle steal mode, the sampling timing is the same regardless of whether the

DREQ is

detected by edge or level. When edge is being detected, however, once sampled it will not be

sampled again until the next edge detection. Once

DREQ input is detected, the next sampling

is not performed until the first state, among those DMAC bus cycles thereby produced, in

which a DACK signal is output (including the detection state itself). The next sampling occurs

immediately prior to the rise edge of the clock pulse(CK) of the third state after the bus cycle

previous to the bus cycle in which the DACK signal is output.

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