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SH7021 Datasheet(PDF) 219 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 219 Page - Renesas Technology Corp |
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219 / 509 page  202 RENESAS CK DREQ DACK Bus cycle Tc Tr Tp Tc CPU CPU CPU DMAC CPU CPU Tc Tr Tp Tc DMAC Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle. Figure 9.19 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = DRAM bus cycle (long pitch normal mode)) CK DREQ DACK Bus cycle Tc Tr Tp Tc CPU DMAC(R) DMAC (R) Tc Tr Tp Tc CPU CPU DMAC (W) CPU DMAC (W) CPU DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle. Figure 9.20 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = DRAM bus cycle (long pitch normal mode)) |
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