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4501 Datasheet(PDF) 140 Page - Renesas Technology Corp

Part # 4501
Description  4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
PDF  212 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4501 Datasheet(HTML) 140 Page - Renesas Technology Corp

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2.3 Timers
2-23
4501 Group
APPLICATION
Rev.2.01
Feb 07, 2005
REJ09B0192-0201
(3)
Timer control register W2
The timer 2 count source selection bits are assigned to bits 0 and 1, the timer 1 count auto-stop
circuit control bit is assigned to bit 2 and the timer 2 control bit is assigned to bit 3.
Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction
can be used to transfer the contents of register W2 to register A.
Table 2.3.3 shows the timer control register W2.
Table 2.3.3 Timer control register W2
Timer control register W2
at reset : 00002
at RAM back-up : state retained
R/W
Stop (state retained)
Operating
Count auto-stop circuit not selected
Count auto-stop circuit selected
Count source
Timer 1 underflow signal
Prescaler output (ORCLK)
CNTR input
System clock
Timer 2 control bit
Timer 1 count auto-stop circuit
control bit (Note 2)
Timer 2 count source selection
bits
W23
W22
W21
W20
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected.
(4)
Timer control register W6
The P12/CNTR function selection bit is assigned to bit 0 and the CNTR output control bit is assigned
to bit 1.
Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction
can be used to transfer the contents of register W6 to register A.
Table 2.3.4 shows the timer control register W6.
Table 2.3.4 Timer control register W6
W21
0
0
1
1
W20
0
1
0
1
Timer control register W6
at reset : 00002
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
P12 (I/O) / CNTR input (Note 2)
P12 (input) / CNTR I/O (Note 2)
Not used
Not used
CNTR output control bit
P12/CNTR function selection bit
W63
W62
W61
W60
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: The CNTR input is valid only when the CNTR input is selected for the timer 2 count source.
3: When timer is used, W63 and W62 are not used.



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