4501 datasheet(144/212 Pages) RENESAS

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2.3 Timers

2-27

4501 Group

APPLICATION

Rev.2.01

Feb 07, 2005

REJ09B0192-0201

Fig. 2.3.4 CNTR output setting example

b3b0

➀ Disable Interrupts

Timer 1 interrupt is temporarily disabled.

Interrupt enable flag INTE

Interrupt control register V1

“0”

✕✕

All interrupts disabled (DI instruction)

Timer 1 interrupt occurrence disabled

(TV1A instruction)

b3b0

0 0

➁ Stop Timer Operation

Timer 1 and prescaler are temporarily stopped.

Dividing ratio of prescaler is selected.

Timer control register W1

Timer 1 stop (TW1A instruction)

Prescaler stop

Prescaler divided by 4 selected

➂ Set Timer Value, Select CNTR Output

CNTR output is selected.

Timer 1 count time is set.

Timer control register W6

Timer 1 reload register R1 “2916”

Timer count value 41 set (T1AB instruction)

✕ 0

CNTR output selected (TW6A instruction)

➃ Clear Interrupt Request

Timer 1 interrupt activated condition is cleared.

Timer 1 interrupt request flag T1F “0”

Timer 1 interrupt activated condition cleared

(SNZT1 instruction)

Note when the interrupt request is cleared

When ➃ is executed, considering the skip of the next instruction according to the

interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.

➄ Start Timer 1 Operation

Timer 1 and prescaler temporarily stopped are restarted.

Timer 1 operation start (TW1A instruction)

Prescaler operation start

1 0

Timer control register W1

➅ Enable Interrupts

The timer 1 interrupt which is temporarily disabled is enabled.

Interrupt control register V1

“1”

Timer 1 interrupt occurrence enabled

(TV1A instruction)

All interrupts enabled (EI instruction)

✕✕

➆ Stop CNTR Output

P12/CNTR I/O port is set to CNTR input port, and it is set to the high-impedance state.

Timer control register W6

CNTR input pin set (TW6A instruction)

✕✕

“✕”: it can be “0” or “1.”

Interrupt enable flag INTE

Input mode is set. (OP1A instruction)

Output latch of port P12

b3b0

✕✕

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