7477 datasheet(68/361 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.11 Interrupts

1-61

(3) Interrupt control register 1 (IE1: Address 00FE16)

Interrupt control register 2 (IE2: Address 00FF16)

The Interrupt control register 1 and the Interrupt control register 2 control the acceptance of interrupt

by source.

Figure 1.11.11 shows a structure of the Interrupt control register 1 and Figure 1.11.12 shows a

structure of an Interrupt control register 2.

Fig. 1.11.11 Structure of Interrupt control register 1

Fig. 1.11.12 Structure of Interrupt control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt control register 1 (IE1) [Address

Name

Function

At reset RW

Interrupt control register 1

0 : Interrupt disabled

1 : Interrupt enabled

Timer 1 interrupt

enable bit

Timer 2 interrupt

enable bit

Timer 3 interrupt

enable bit

Timer 4 interrupt

enable bit

Note:

Serial I/O receive interrupt

enable bit (7477/7478

group) (Note)

A-D conversion completion

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Serial I/O interrupt enable

bit (7470/7471 group)

Serial I/O transmit interrupt

enable bit (7477/7478 group)

Nothing is allocated for this bit. This is write

disabled bit and is undefined at reading.

In the 7470/7471 group, Nothing is allocated for bit 5.

This is write disabled bit and undefined at reading.

00FE16]

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt control register 2 (IE2) [Address

Name

Function

At reset RW

Interrupt control register 2

0 : Interrupt disabled

1 : Interrupt enabled

INT0 interrupt enable

bit

INT1 interrupt enable

bit

CNTR0 or CNTR1

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Nothing is allocated for these bits. There are write

disabled bits and are undefined at reading.

00FF16]

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